Modern digital electronic circuits rely upon the delivery of significant currents to achieve required power for operation, as the trend has been toward lower voltages. This presents a dilemma in circuit design. Delivering high current loads, e.g., hundreds of amps, to printed circuit boards and integrated circuit devices can raise the cost of circuits. High current buses add significant expense to circuits and devices, but are generally necessary to deliver high current to printed circuit boards.
Modern microprocessors highlight the trend toward delivery of high current loads. The Pentium® II processor, introduced in the late 1990s, marked the trend toward requiring high current at low voltage. This has continued through the Pentium® line of processors. Switching power supplies of a category now termed “voltage regulator modules,” first introduced in the 1980s, became popular with this generation of processors and their high current at low voltage demands. Commercial voltage regulator modules used with these types of processors use parallel conversion circuits and seek to enforce current sharing among the parallel converters through actively monitored controls. A typical Pentium® IV processor uses four converters to deliver less than 2 V, from either a 5V or 12V source. Future generations of processors are likely to require hundreds of amps at voltages as low as 1V or lower. Server applications often make use of even higher source voltages, e.g., 48V. For extreme voltage conversion ratios, such as 48 V to 1 V, two-stage conversion processes have become conventional. In these cases, a one-stage conversion would be preferable to a two-stage conversion, as power losses and other problems are exacerbated by multi-stage conversion.
The switch operation in conventional parallel converters is normally interleaved. The main switches in n converters are spaced in phase by 1/n of each cycle. This reduces output voltage ripple by a factor of n relative to each converter and provides some dynamic advantages. Success in this scheme requires current sharing among the parallel converters, as imperfect current sharing can result in the overloading of an individual converter. This difficulty has been an active subject of research, with the active monitoring and control mentioned above being explored extensively. Despite the research, there remains a need for a converter that supports current sharing, one-stage conversion and performs well during fast transients.